50_a_paulfellows
n50_a_paulfellows
n50_a_paulfellows__1_1_1
There
n50_a_paulfellows__1_2_1
's
n50_a_paulfellows__1_3_1_1
an
n50_a_paulfellows__1_3_2_1_1
awful
n50_a_paulfellows__1_3_3_1
lot
n50_a_paulfellows__1_3_4_1_1
of
n50_a_paulfellows__1_3_4_2_1_1
components
n50_a_paulfellows__1_4_1_1
on
n50_a_paulfellows__1_4_2_1_1
there
n50_a_paulfellows__1_5_1_1
by
n50_a_paulfellows__1_5_2_1_1_1
today
n50_a_paulfellows__1_5_2_1_2_1
's
n50_a_paulfellows__1_5_2_2_1
standards
n50_a_paulfellows__1_6_1
,
n50_a_paulfellows__1_7_1_1_1_1
I
n50_a_paulfellows__1_7_1_2_1
think
n50_a_paulfellows__1_7_1_3_1_1_1_1
it
n50_a_paulfellows__1_7_1_3_1_2_1
broke
n50_a_paulfellows__1_7_1_3_1_3_1_1
the
n50_a_paulfellows__1_7_1_3_1_3_2_1
CAD
n50_a_paulfellows__1_7_1_3_1_3_3_1
program
n50_a_paulfellows__1_7_1_3_1_4_1_1
because
n50_a_paulfellows__1_7_1_3_1_4_2_1_1
there
n50_a_paulfellows__1_7_1_3_1_4_2_2_1
were
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_1_1
more
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_1_1
than
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_2_1_1
512
n50_a_paulfellows__1_7_1_4_1
,
n50_a_paulfellows__1_7_1_5_1_1_1_1
the
n50_a_paulfellows__1_7_1_5_1_1_2_1
CAD
n50_a_paulfellows__1_7_1_5_1_1_3_1
program
n50_a_paulfellows__1_7_1_5_1_1_4_1_1
that
n50_a_paulfellows__1_7_1_5_1_1_4_2_1_1
the
n50_a_paulfellows__1_7_1_5_1_1_4_2_2_1
guys
n50_a_paulfellows__1_7_1_5_1_1_4_3_1
were
n50_a_paulfellows__1_7_1_5_1_1_4_4_1_1
trying
n50_a_paulfellows__1_7_1_5_1_1_4_4_2_1_1
*T*
n50_a_paulfellows__1_7_1_5_1_1_4_4_2_2_1
to
n50_a_paulfellows__1_7_1_5_1_1_4_4_2_3_1
use
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_1_1
to
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_2_1
design
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3_1_1
the
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3_2_1
hardware
n50_a_paulfellows__1_7_1_5_1_2_1
could
n50_a_paulfellows__1_7_1_5_1_3_1
n't
n50_a_paulfellows__1_7_1_5_1_4_1_1
handle
n50_a_paulfellows__1_7_1_5_1_4_2_1_1
it
n50_a_paulfellows__1_8_1
.
n50_a_paulfellows__1
IP-MAT
n50_a_paulfellows__1_1
EX
n50_a_paulfellows__1->n50_a_paulfellows__1_1
n50_a_paulfellows__1_2
BEP;_ex_V_
n50_a_paulfellows__1->n50_a_paulfellows__1_2
n50_a_paulfellows__1_3
NP-ESBJ
n50_a_paulfellows__1->n50_a_paulfellows__1_3
n50_a_paulfellows__1_4
PP-NIM
n50_a_paulfellows__1->n50_a_paulfellows__1_4
n50_a_paulfellows__1_5
PP-NIM
n50_a_paulfellows__1->n50_a_paulfellows__1_5
n50_a_paulfellows__1_6
PUNC
n50_a_paulfellows__1->n50_a_paulfellows__1_6
n50_a_paulfellows__1_7
PRN
n50_a_paulfellows__1->n50_a_paulfellows__1_7
n50_a_paulfellows__1_8
PUNC
n50_a_paulfellows__1->n50_a_paulfellows__1_8
n50_a_paulfellows__1_1->n50_a_paulfellows__1_1_1
n50_a_paulfellows__1_2->n50_a_paulfellows__1_2_1
n50_a_paulfellows__1_3_1
D
n50_a_paulfellows__1_3->n50_a_paulfellows__1_3_1
n50_a_paulfellows__1_3_2
ADJP
n50_a_paulfellows__1_3->n50_a_paulfellows__1_3_2
n50_a_paulfellows__1_3_3
N
n50_a_paulfellows__1_3->n50_a_paulfellows__1_3_3
n50_a_paulfellows__1_3_4
PP
n50_a_paulfellows__1_3->n50_a_paulfellows__1_3_4
n50_a_paulfellows__1_3_1->n50_a_paulfellows__1_3_1_1
n50_a_paulfellows__1_3_2_1
ADJ
n50_a_paulfellows__1_3_2->n50_a_paulfellows__1_3_2_1
n50_a_paulfellows__1_3_2_1->n50_a_paulfellows__1_3_2_1_1
n50_a_paulfellows__1_3_3->n50_a_paulfellows__1_3_3_1
n50_a_paulfellows__1_3_4_1
P-ROLE
n50_a_paulfellows__1_3_4->n50_a_paulfellows__1_3_4_1
n50_a_paulfellows__1_3_4_2
NP
n50_a_paulfellows__1_3_4->n50_a_paulfellows__1_3_4_2
n50_a_paulfellows__1_3_4_1->n50_a_paulfellows__1_3_4_1_1
n50_a_paulfellows__1_3_4_2_1
NS
n50_a_paulfellows__1_3_4_2->n50_a_paulfellows__1_3_4_2_1
n50_a_paulfellows__1_3_4_2_1->n50_a_paulfellows__1_3_4_2_1_1
n50_a_paulfellows__1_4_1
P-ROLE
n50_a_paulfellows__1_4->n50_a_paulfellows__1_4_1
n50_a_paulfellows__1_4_2
ADVP
n50_a_paulfellows__1_4->n50_a_paulfellows__1_4_2
n50_a_paulfellows__1_4_1->n50_a_paulfellows__1_4_1_1
n50_a_paulfellows__1_4_2_1
ADV
n50_a_paulfellows__1_4_2->n50_a_paulfellows__1_4_2_1
n50_a_paulfellows__1_4_2_1->n50_a_paulfellows__1_4_2_1_1
n50_a_paulfellows__1_5_1
P-ROLE
n50_a_paulfellows__1_5->n50_a_paulfellows__1_5_1
n50_a_paulfellows__1_5_2
NP
n50_a_paulfellows__1_5->n50_a_paulfellows__1_5_2
n50_a_paulfellows__1_5_1->n50_a_paulfellows__1_5_1_1
n50_a_paulfellows__1_5_2_1
NP-GEN
n50_a_paulfellows__1_5_2->n50_a_paulfellows__1_5_2_1
n50_a_paulfellows__1_5_2_2
NS
n50_a_paulfellows__1_5_2->n50_a_paulfellows__1_5_2_2
n50_a_paulfellows__1_5_2_1_1
N
n50_a_paulfellows__1_5_2_1->n50_a_paulfellows__1_5_2_1_1
n50_a_paulfellows__1_5_2_1_2
GENM
n50_a_paulfellows__1_5_2_1->n50_a_paulfellows__1_5_2_1_2
n50_a_paulfellows__1_5_2_1_1->n50_a_paulfellows__1_5_2_1_1_1
n50_a_paulfellows__1_5_2_1_2->n50_a_paulfellows__1_5_2_1_2_1
n50_a_paulfellows__1_5_2_2->n50_a_paulfellows__1_5_2_2_1
n50_a_paulfellows__1_6->n50_a_paulfellows__1_6_1
n50_a_paulfellows__1_7_1
IP-MAT
n50_a_paulfellows__1_7->n50_a_paulfellows__1_7_1
n50_a_paulfellows__1_7_1_1
NP-SBJ
n50_a_paulfellows__1_7_1->n50_a_paulfellows__1_7_1_1
n50_a_paulfellows__1_7_1_2
VBP;__
n50_a_paulfellows__1_7_1->n50_a_paulfellows__1_7_1_2
n50_a_paulfellows__1_7_1_3
CP-THT-OB1
n50_a_paulfellows__1_7_1->n50_a_paulfellows__1_7_1_3
n50_a_paulfellows__1_7_1_4
PUNC
n50_a_paulfellows__1_7_1->n50_a_paulfellows__1_7_1_4
n50_a_paulfellows__1_7_1_5
PRN
n50_a_paulfellows__1_7_1->n50_a_paulfellows__1_7_1_5
n50_a_paulfellows__1_7_1_1_1
PRO
n50_a_paulfellows__1_7_1_1->n50_a_paulfellows__1_7_1_1_1
n50_a_paulfellows__1_7_1_1_1->n50_a_paulfellows__1_7_1_1_1_1
n50_a_paulfellows__1_7_1_2->n50_a_paulfellows__1_7_1_2_1
n50_a_paulfellows__1_7_1_3_1
IP-SUB
n50_a_paulfellows__1_7_1_3->n50_a_paulfellows__1_7_1_3_1
n50_a_paulfellows__1_7_1_3_1_1
NP-SBJ
n50_a_paulfellows__1_7_1_3_1->n50_a_paulfellows__1_7_1_3_1_1
n50_a_paulfellows__1_7_1_3_1_2
VBD;__
n50_a_paulfellows__1_7_1_3_1->n50_a_paulfellows__1_7_1_3_1_2
n50_a_paulfellows__1_7_1_3_1_3
NP-OB1
n50_a_paulfellows__1_7_1_3_1->n50_a_paulfellows__1_7_1_3_1_3
n50_a_paulfellows__1_7_1_3_1_4
PP-SCON
n50_a_paulfellows__1_7_1_3_1->n50_a_paulfellows__1_7_1_3_1_4
n50_a_paulfellows__1_7_1_3_1_1_1
PRO
n50_a_paulfellows__1_7_1_3_1_1->n50_a_paulfellows__1_7_1_3_1_1_1
n50_a_paulfellows__1_7_1_3_1_1_1->n50_a_paulfellows__1_7_1_3_1_1_1_1
n50_a_paulfellows__1_7_1_3_1_2->n50_a_paulfellows__1_7_1_3_1_2_1
n50_a_paulfellows__1_7_1_3_1_3_1
D
n50_a_paulfellows__1_7_1_3_1_3->n50_a_paulfellows__1_7_1_3_1_3_1
n50_a_paulfellows__1_7_1_3_1_3_2
NPR
n50_a_paulfellows__1_7_1_3_1_3->n50_a_paulfellows__1_7_1_3_1_3_2
n50_a_paulfellows__1_7_1_3_1_3_3
N
n50_a_paulfellows__1_7_1_3_1_3->n50_a_paulfellows__1_7_1_3_1_3_3
n50_a_paulfellows__1_7_1_3_1_3_1->n50_a_paulfellows__1_7_1_3_1_3_1_1
n50_a_paulfellows__1_7_1_3_1_3_2->n50_a_paulfellows__1_7_1_3_1_3_2_1
n50_a_paulfellows__1_7_1_3_1_3_3->n50_a_paulfellows__1_7_1_3_1_3_3_1
n50_a_paulfellows__1_7_1_3_1_4_1
P-CONN
n50_a_paulfellows__1_7_1_3_1_4->n50_a_paulfellows__1_7_1_3_1_4_1
n50_a_paulfellows__1_7_1_3_1_4_2
IP-ADV
n50_a_paulfellows__1_7_1_3_1_4->n50_a_paulfellows__1_7_1_3_1_4_2
n50_a_paulfellows__1_7_1_3_1_4_1->n50_a_paulfellows__1_7_1_3_1_4_1_1
n50_a_paulfellows__1_7_1_3_1_4_2_1
EX
n50_a_paulfellows__1_7_1_3_1_4_2->n50_a_paulfellows__1_7_1_3_1_4_2_1
n50_a_paulfellows__1_7_1_3_1_4_2_2
BED;_ex_V_
n50_a_paulfellows__1_7_1_3_1_4_2->n50_a_paulfellows__1_7_1_3_1_4_2_2
n50_a_paulfellows__1_7_1_3_1_4_2_3
NP-ESBJ
n50_a_paulfellows__1_7_1_3_1_4_2->n50_a_paulfellows__1_7_1_3_1_4_2_3
n50_a_paulfellows__1_7_1_3_1_4_2_1->n50_a_paulfellows__1_7_1_3_1_4_2_1_1
n50_a_paulfellows__1_7_1_3_1_4_2_2->n50_a_paulfellows__1_7_1_3_1_4_2_2_1
n50_a_paulfellows__1_7_1_3_1_4_2_3_1
ADJP
n50_a_paulfellows__1_7_1_3_1_4_2_3->n50_a_paulfellows__1_7_1_3_1_4_2_3_1
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_1
ADJR
n50_a_paulfellows__1_7_1_3_1_4_2_3_1->n50_a_paulfellows__1_7_1_3_1_4_2_3_1_1
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2
PP
n50_a_paulfellows__1_7_1_3_1_4_2_3_1->n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_1->n50_a_paulfellows__1_7_1_3_1_4_2_3_1_1_1
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_1
P-ROLE
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2->n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_1
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_2
NP
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2->n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_2
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_1->n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_1_1
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_2_1
NUM
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_2->n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_2_1
n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_2_1->n50_a_paulfellows__1_7_1_3_1_4_2_3_1_2_2_1_1
n50_a_paulfellows__1_7_1_4->n50_a_paulfellows__1_7_1_4_1
n50_a_paulfellows__1_7_1_5_1
IP-MAT
n50_a_paulfellows__1_7_1_5->n50_a_paulfellows__1_7_1_5_1
n50_a_paulfellows__1_7_1_5_1_1
NP-SBJ
n50_a_paulfellows__1_7_1_5_1->n50_a_paulfellows__1_7_1_5_1_1
n50_a_paulfellows__1_7_1_5_1_2
MD;_cat_Vi_
n50_a_paulfellows__1_7_1_5_1->n50_a_paulfellows__1_7_1_5_1_2
n50_a_paulfellows__1_7_1_5_1_3
NEG;_clitic_
n50_a_paulfellows__1_7_1_5_1->n50_a_paulfellows__1_7_1_5_1_3
n50_a_paulfellows__1_7_1_5_1_4
IP-INF-CAT
n50_a_paulfellows__1_7_1_5_1->n50_a_paulfellows__1_7_1_5_1_4
n50_a_paulfellows__1_7_1_5_1_1_1
D
n50_a_paulfellows__1_7_1_5_1_1->n50_a_paulfellows__1_7_1_5_1_1_1
n50_a_paulfellows__1_7_1_5_1_1_2
NPR
n50_a_paulfellows__1_7_1_5_1_1->n50_a_paulfellows__1_7_1_5_1_1_2
n50_a_paulfellows__1_7_1_5_1_1_3
N
n50_a_paulfellows__1_7_1_5_1_1->n50_a_paulfellows__1_7_1_5_1_1_3
n50_a_paulfellows__1_7_1_5_1_1_4
IP-REL
n50_a_paulfellows__1_7_1_5_1_1->n50_a_paulfellows__1_7_1_5_1_1_4
n50_a_paulfellows__1_7_1_5_1_1_1->n50_a_paulfellows__1_7_1_5_1_1_1_1
n50_a_paulfellows__1_7_1_5_1_1_2->n50_a_paulfellows__1_7_1_5_1_1_2_1
n50_a_paulfellows__1_7_1_5_1_1_3->n50_a_paulfellows__1_7_1_5_1_1_3_1
n50_a_paulfellows__1_7_1_5_1_1_4_1
C
n50_a_paulfellows__1_7_1_5_1_1_4->n50_a_paulfellows__1_7_1_5_1_1_4_1
n50_a_paulfellows__1_7_1_5_1_1_4_2
NP-SBJ
n50_a_paulfellows__1_7_1_5_1_1_4->n50_a_paulfellows__1_7_1_5_1_1_4_2
n50_a_paulfellows__1_7_1_5_1_1_4_3
BED;_cat_Vg_
n50_a_paulfellows__1_7_1_5_1_1_4->n50_a_paulfellows__1_7_1_5_1_1_4_3
n50_a_paulfellows__1_7_1_5_1_1_4_4
IP-PPL-CAT
n50_a_paulfellows__1_7_1_5_1_1_4->n50_a_paulfellows__1_7_1_5_1_1_4_4
n50_a_paulfellows__1_7_1_5_1_1_4_5
PP-SCON
n50_a_paulfellows__1_7_1_5_1_1_4->n50_a_paulfellows__1_7_1_5_1_1_4_5
n50_a_paulfellows__1_7_1_5_1_1_4_1->n50_a_paulfellows__1_7_1_5_1_1_4_1_1
n50_a_paulfellows__1_7_1_5_1_1_4_2_1
D
n50_a_paulfellows__1_7_1_5_1_1_4_2->n50_a_paulfellows__1_7_1_5_1_1_4_2_1
n50_a_paulfellows__1_7_1_5_1_1_4_2_2
NS
n50_a_paulfellows__1_7_1_5_1_1_4_2->n50_a_paulfellows__1_7_1_5_1_1_4_2_2
n50_a_paulfellows__1_7_1_5_1_1_4_2_1->n50_a_paulfellows__1_7_1_5_1_1_4_2_1_1
n50_a_paulfellows__1_7_1_5_1_1_4_2_2->n50_a_paulfellows__1_7_1_5_1_1_4_2_2_1
n50_a_paulfellows__1_7_1_5_1_1_4_3->n50_a_paulfellows__1_7_1_5_1_1_4_3_1
n50_a_paulfellows__1_7_1_5_1_1_4_4_1
VAG;_It_
n50_a_paulfellows__1_7_1_5_1_1_4_4->n50_a_paulfellows__1_7_1_5_1_1_4_4_1
n50_a_paulfellows__1_7_1_5_1_1_4_4_2
IP-INF-CLR
n50_a_paulfellows__1_7_1_5_1_1_4_4->n50_a_paulfellows__1_7_1_5_1_1_4_4_2
n50_a_paulfellows__1_7_1_5_1_1_4_4_1->n50_a_paulfellows__1_7_1_5_1_1_4_4_1_1
n50_a_paulfellows__1_7_1_5_1_1_4_4_2_1
NP-OB1
n50_a_paulfellows__1_7_1_5_1_1_4_4_2->n50_a_paulfellows__1_7_1_5_1_1_4_4_2_1
n50_a_paulfellows__1_7_1_5_1_1_4_4_2_2
TO
n50_a_paulfellows__1_7_1_5_1_1_4_4_2->n50_a_paulfellows__1_7_1_5_1_1_4_4_2_2
n50_a_paulfellows__1_7_1_5_1_1_4_4_2_3
VB;_Tn_
n50_a_paulfellows__1_7_1_5_1_1_4_4_2->n50_a_paulfellows__1_7_1_5_1_1_4_4_2_3
n50_a_paulfellows__1_7_1_5_1_1_4_4_2_1->n50_a_paulfellows__1_7_1_5_1_1_4_4_2_1_1
n50_a_paulfellows__1_7_1_5_1_1_4_4_2_2->n50_a_paulfellows__1_7_1_5_1_1_4_4_2_2_1
n50_a_paulfellows__1_7_1_5_1_1_4_4_2_3->n50_a_paulfellows__1_7_1_5_1_1_4_4_2_3_1
n50_a_paulfellows__1_7_1_5_1_1_4_5_1
IP-INF
n50_a_paulfellows__1_7_1_5_1_1_4_5->n50_a_paulfellows__1_7_1_5_1_1_4_5_1
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_1
TO
n50_a_paulfellows__1_7_1_5_1_1_4_5_1->n50_a_paulfellows__1_7_1_5_1_1_4_5_1_1
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_2
VB;_Tn_
n50_a_paulfellows__1_7_1_5_1_1_4_5_1->n50_a_paulfellows__1_7_1_5_1_1_4_5_1_2
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3
NP-OB1
n50_a_paulfellows__1_7_1_5_1_1_4_5_1->n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_1->n50_a_paulfellows__1_7_1_5_1_1_4_5_1_1_1
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_2->n50_a_paulfellows__1_7_1_5_1_1_4_5_1_2_1
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3_1
D
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3->n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3_1
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3_2
N
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3->n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3_2
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3_1->n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3_1_1
n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3_2->n50_a_paulfellows__1_7_1_5_1_1_4_5_1_3_2_1
n50_a_paulfellows__1_7_1_5_1_2->n50_a_paulfellows__1_7_1_5_1_2_1
n50_a_paulfellows__1_7_1_5_1_3->n50_a_paulfellows__1_7_1_5_1_3_1
n50_a_paulfellows__1_7_1_5_1_4_1
VB;_Tn_
n50_a_paulfellows__1_7_1_5_1_4->n50_a_paulfellows__1_7_1_5_1_4_1
n50_a_paulfellows__1_7_1_5_1_4_2
NP-OB1
n50_a_paulfellows__1_7_1_5_1_4->n50_a_paulfellows__1_7_1_5_1_4_2
n50_a_paulfellows__1_7_1_5_1_4_1->n50_a_paulfellows__1_7_1_5_1_4_1_1
n50_a_paulfellows__1_7_1_5_1_4_2_1
PRO
n50_a_paulfellows__1_7_1_5_1_4_2->n50_a_paulfellows__1_7_1_5_1_4_2_1
n50_a_paulfellows__1_7_1_5_1_4_2_1->n50_a_paulfellows__1_7_1_5_1_4_2_1_1
n50_a_paulfellows__1_8->n50_a_paulfellows__1_8_1
( (IP-MAT (EX There;{there})
(BEP;_ex_V_ <apos>s;{be})
(NP-ESBJ (D an;{an})
(ADJP (ADJ awful;{awful}))
(N lot;{lot})
(PP (P-ROLE of;{of})
(NP (NS components;{component}))))
(PP-NIM (P-ROLE on;{on})
(ADVP (ADV there;{there})))
(PP-NIM (P-ROLE by;{by})
(NP (NP-GEN (N today;{today})
(GENM <apos>s))
(NS standards;{standard})))
(PUNC ,)
(PRN (IP-MAT (NP-SBJ (PRO I;{I}))
(VBP;__ think;{think})
(CP-THT-OB1 (IP-SUB (NP-SBJ (PRO it;{it}))
(VBD;__ broke;{break})
(NP-OB1 (D the;{the})
(NPR CAD;{CAD})
(N program;{program}))
(PP-SCON (P-CONN because;{because})
(IP-ADV (EX there;{there})
(BED;_ex_V_ were;{be})
(NP-ESBJ (ADJP (ADJR more;{more})
(PP (P-ROLE than;{than})
(NP (NUM 512)))))))))
(PUNC ,)
(PRN (IP-MAT (NP-SBJ (D the;{the})
(NPR CAD;{CAD})
(N program;{program})
(IP-REL (C that;{that})
(NP-SBJ (D the;{the})
(NS guys;{guy}))
(BED;_cat_Vg_ were;{be})
(IP-PPL-CAT (VAG;_It_ trying;{try})
(IP-INF-CLR (NP-OB1 *T*)
(TO to;{to})
(VB;_Tn_ use;{use})))
(PP-SCON (IP-INF (TO to;{to})
(VB;_Tn_ design;{design})
(NP-OB1;{HARDWARE} (D the;{the})
(N hardware;{hardware}))))))
(MD;_cat_Vi_ could;{can})
(NEG;_clitic_ n<apos>t;{not})
(IP-INF-CAT (VB;_Tn_ handle;{handle})
(NP-OB1;{HARDWARE} (PRO it;{it})))))))
(PUNC .))
(ID 50_a_paulfellows))
%3
z_0050_5014
r_0050_0040__design
design
z_0050_5014->r_0050_0040__design
[restriction]
r_0050_0035__were
were
z_0050_5014->r_0050_0035__were
[scope]
r_0050_0041__the_r_0050_0042__hardware
the hardware
r_0050_0040__design->r_0050_0041__the_r_0050_0042__hardware
[arg1]
r_0050_0033__the_r_0050_0034__guys
the guys
r_0050_0040__design->r_0050_0033__the_r_0050_0034__guys
[arg0]
r_0050_0036__trying
trying
r_0050_0035__were->r_0050_0036__trying
[scope]
z_0050_5008
r_0050_0025__more
more
z_0050_5008->r_0050_0025__more
[attrib]
r_0050_0027__512
512
r_0050_0025__more->r_0050_0027__512
than
r_0050_0045__handle
handle
r_0050_0045__handle->r_0050_0041__the_r_0050_0042__hardware
[arg1]
r_0050_0029__the_r_0050_0030__CAD_r_0050_0031__program
the CAD program
r_0050_0045__handle->r_0050_0029__the_r_0050_0030__CAD_r_0050_0031__program
[arg0]
r_0050_0044__n_apos_t
n't
r_0050_0043__could
could
r_0050_0044__n_apos_t->r_0050_0043__could
[keep_scope]
r_0050_0043__could->r_0050_0045__handle
[scope]
r_0050_0038__use
use
r_0050_0038__use->r_0050_0029__the_r_0050_0030__CAD_r_0050_0031__program
[inv_arg1]
r_0050_0038__use->r_0050_0033__the_r_0050_0034__guys
[arg0]
r_0050_0036__trying->r_0050_0033__the_r_0050_0034__guys
[arg0]
r_0050_0036__trying->r_0050_0038__use
[clr]
r_0050_0024__were
were
r_0050_0024__were->z_0050_5008
[arg0]
r_0050_0022__because
because
r_0050_0022__because->r_0050_0024__were
[restriction]
r_0050_0018__broke
broke
r_0050_0022__because->r_0050_0018__broke
[scope]
r_0050_0019__the_r_0050_0020__CAD_r_0050_0021__program
the CAD program
r_0050_0018__broke->r_0050_0019__the_r_0050_0020__CAD_r_0050_0021__program
[arg1]
r_0050_0017__it
it
r_0050_0018__broke->r_0050_0017__it
[arg0]
r_0050_0016__think
think
r_0050_0016__think->r_0050_0044__n_apos_t
[prn]
r_0050_0016__think->r_0050_0022__because
[arg1]
r_0050_0015__I
I
r_0050_0016__think->r_0050_0015__I
[arg0]
r_0050_0013__standards
standards
r_0050_0011__today
today
r_0050_0013__standards->r_0050_0011__today
[gen]
r_0050_0003__an_r_0050_0005__lot
an lot
r_0050_0007__components
components
r_0050_0003__an_r_0050_0005__lot->r_0050_0007__components
of
r_0050_0004__awful
awful
r_0050_0003__an_r_0050_0005__lot->r_0050_0004__awful
[attrib]
r_0050_0002___apos_s
's
r_0050_0002___apos_s->r_0050_0016__think
[prn]
r_0050_0002___apos_s->r_0050_0013__standards
by [nim]
r_0050_0002___apos_s->r_0050_0003__an_r_0050_0005__lot
[arg0]
r_0050_0009__there
there
r_0050_0002___apos_s->r_0050_0009__there
on [nim]
arc(r_0050_0002___apos_s,r_0050_0003__an_r_0050_0005__lot,arg0).
arc(r_0050_0002___apos_s,r_0050_0009__there,r_0050_0008__on__nim).
arc(r_0050_0002___apos_s,r_0050_0013__standards,r_0050_0010__by__nim).
arc(r_0050_0002___apos_s,r_0050_0016__think,prn).
arc(r_0050_0003__an_r_0050_0005__lot,r_0050_0004__awful,attrib).
arc(r_0050_0003__an_r_0050_0005__lot,r_0050_0007__components,r_0050_0006__of).
arc(r_0050_0013__standards,r_0050_0011__today,gen).
arc(r_0050_0016__think,r_0050_0015__I,arg0).
arc(r_0050_0016__think,r_0050_0022__because,arg1).
arc(r_0050_0016__think,r_0050_0044__n_apos_t,prn).
arc(r_0050_0018__broke,r_0050_0017__it,arg0).
arc(r_0050_0018__broke,r_0050_0019__the_r_0050_0020__CAD_r_0050_0021__program,arg1).
arc(r_0050_0022__because,r_0050_0018__broke,scope).
arc(r_0050_0022__because,r_0050_0024__were,restriction).
arc(r_0050_0024__were,z_0050_5008,arg0).
arc(r_0050_0025__more,r_0050_0027__512,r_0050_0026__than).
arc(r_0050_0035__were,r_0050_0036__trying,scope).
arc(r_0050_0036__trying,r_0050_0033__the_r_0050_0034__guys,arg0).
arc(r_0050_0036__trying,r_0050_0038__use,clr).
arc(r_0050_0038__use,r_0050_0029__the_r_0050_0030__CAD_r_0050_0031__program,inv_arg1).
arc(r_0050_0038__use,r_0050_0033__the_r_0050_0034__guys,arg0).
arc(r_0050_0040__design,r_0050_0033__the_r_0050_0034__guys,arg0).
arc(r_0050_0040__design,r_0050_0041__the_r_0050_0042__hardware,arg1).
arc(r_0050_0043__could,r_0050_0045__handle,scope).
arc(r_0050_0044__n_apos_t,r_0050_0043__could,keep_scope).
arc(r_0050_0045__handle,r_0050_0029__the_r_0050_0030__CAD_r_0050_0031__program,arg0).
arc(r_0050_0045__handle,r_0050_0041__the_r_0050_0042__hardware,arg1).
arc(z_0050_5008,r_0050_0025__more,attrib).
arc(z_0050_5014,r_0050_0035__were,scope).
arc(z_0050_5014,r_0050_0040__design,restriction).
%3
r_0050_0002___apos_s
's
r_0050_0003__an_r_0050_0005__lot
an lot
r_0050_0002___apos_s->r_0050_0003__an_r_0050_0005__lot
[arg0]
r_0050_0009__there
there
r_0050_0002___apos_s->r_0050_0009__there
on [nim]
r_0050_0013__standards
standards
r_0050_0002___apos_s->r_0050_0013__standards
by [nim]
r_0050_0016__think
think
r_0050_0002___apos_s->r_0050_0016__think
[prn]
r_0050_0004__awful
awful
r_0050_0003__an_r_0050_0005__lot->r_0050_0004__awful
[attrib]
r_0050_0007__components
components
r_0050_0003__an_r_0050_0005__lot->r_0050_0007__components
of
r_0050_0011__today
today
r_0050_0013__standards->r_0050_0011__today
[gen]
r_0050_0015__I
I
r_0050_0016__think->r_0050_0015__I
[arg0]
r_0050_0022__because
because
r_0050_0016__think->r_0050_0022__because
[arg1]
r_0050_0044__n_apos_t
n't
r_0050_0016__think->r_0050_0044__n_apos_t
[prn]
r_0050_0018__broke
broke
r_0050_0022__because->r_0050_0018__broke
[conj2]
r_0050_0024__were
were
r_0050_0022__because->r_0050_0024__were
[conj1]
r_0050_0043__could_r_0050_0045__handle
could handle
r_0050_0044__n_apos_t->r_0050_0043__could_r_0050_0045__handle
[keep_scope]
r_0050_0017__it
it
r_0050_0018__broke->r_0050_0017__it
[arg0]
r_0050_0019__the_r_0050_0020__CAD_r_0050_0021__program
the CAD program
r_0050_0018__broke->r_0050_0019__the_r_0050_0020__CAD_r_0050_0021__program
[arg1]
z_0050_5008
r_0050_0024__were->z_0050_5008
[arg0]
r_0050_0025__more
more
z_0050_5008->r_0050_0025__more
[attrib]
r_0050_0027__512
512
r_0050_0025__more->r_0050_0027__512
than
r_0050_0035__were_r_0050_0036__trying
were trying
r_0050_0033__the_r_0050_0034__guys
the guys
r_0050_0035__were_r_0050_0036__trying->r_0050_0033__the_r_0050_0034__guys
[arg0]
r_0050_0038__use
use
r_0050_0035__were_r_0050_0036__trying->r_0050_0038__use
[clr]
r_0050_0038__use->r_0050_0033__the_r_0050_0034__guys
[arg0]
r_0050_0029__the_r_0050_0030__CAD_r_0050_0031__program
the CAD program
r_0050_0029__the_r_0050_0030__CAD_r_0050_0031__program->r_0050_0038__use
[inv_arg1]
r_0050_0040__design
design
r_0050_0040__design->r_0050_0033__the_r_0050_0034__guys
[arg0]
r_0050_0041__the_r_0050_0042__hardware
the hardware
r_0050_0040__design->r_0050_0041__the_r_0050_0042__hardware
[arg1]
r_0050_0043__could_r_0050_0045__handle->r_0050_0029__the_r_0050_0030__CAD_r_0050_0031__program
[arg0]
r_0050_0043__could_r_0050_0045__handle->r_0050_0041__the_r_0050_0042__hardware
[arg1]
z_0050_5014
z_0050_5014->r_0050_0035__were_r_0050_0036__trying
[conj2]
z_0050_5014->r_0050_0040__design
[conj1]
fof(formula,axiom,
? [R_0050_0004__AWFUL,R_0050_0007__COMPONENTS,R_0050_0003__AN_R_0050_0005__LOT,R_0050_0009__THERE,R_0050_0011__TODAY,R_0050_0013__STANDARDS,R_0050_0015__I,R_0050_0017__IT,R_0050_0019__THE_R_0050_0020__CAD_R_0050_0021__PROGRAM,R_0050_0018__BROKE,R_0050_0027__512,R_0050_0025__MORE,Z_0050_5008,R_0050_0024__WERE,R_0050_0022__BECAUSE,R_0050_0016__THINK,R_0050_0002___APOS_S,R_0050_0033__THE_R_0050_0034__GUYS,R_0050_0038__USE,R_0050_0035__WERE_R_0050_0036__TRYING,R_0050_0041__THE_R_0050_0042__HARDWARE,R_0050_0040__DESIGN,Z_0050_5014] :
( r_0050_0004__awful(R_0050_0004__AWFUL)
& r_0050_0007__components(R_0050_0007__COMPONENTS)
& r_0050_0009__there(R_0050_0009__THERE)
& r_0050_0011__today(R_0050_0011__TODAY)
& r_0050_0015__I(R_0050_0015__I)
& r_0050_0017__it(R_0050_0017__IT)
& r_0050_0019__the_r_0050_0020__CAD_r_0050_0021__program(R_0050_0019__THE_R_0050_0020__CAD_R_0050_0021__PROGRAM)
& r_0050_0027__512(R_0050_0027__512)
& r_0050_0033__the_r_0050_0034__guys(R_0050_0033__THE_R_0050_0034__GUYS)
& r_0050_0041__the_r_0050_0042__hardware(R_0050_0041__THE_R_0050_0042__HARDWARE)
& z_0050_5014(Z_0050_5014)
& has_conj1(Z_0050_5014,R_0050_0040__DESIGN)
& r_0050_0040__design(R_0050_0040__DESIGN)
& has_arg1(R_0050_0040__DESIGN,R_0050_0041__THE_R_0050_0042__HARDWARE)
& has_arg0(R_0050_0040__DESIGN,R_0050_0033__THE_R_0050_0034__GUYS)
& has_conj2(Z_0050_5014,R_0050_0035__WERE_R_0050_0036__TRYING)
& r_0050_0035__were_r_0050_0036__trying(R_0050_0035__WERE_R_0050_0036__TRYING)
& has_clr(R_0050_0035__WERE_R_0050_0036__TRYING,R_0050_0038__USE)
& r_0050_0038__use(R_0050_0038__USE)
& has_arg0(R_0050_0038__USE,R_0050_0033__THE_R_0050_0034__GUYS)
& has_arg0(R_0050_0035__WERE_R_0050_0036__TRYING,R_0050_0033__THE_R_0050_0034__GUYS)
& r_0050_0002___apos_s(R_0050_0002___APOS_S)
& has_prn(R_0050_0002___APOS_S,R_0050_0016__THINK)
& r_0050_0016__think(R_0050_0016__THINK)
& has_prn(R_0050_0016__THINK,R_0050_0044__N_APOS_T)
& ~ ? [R_0050_0029__THE_R_0050_0030__CAD_R_0050_0031__PROGRAM,R_0050_0043__COULD_R_0050_0045__HANDLE] :
( r_0050_0043__could_r_0050_0045__handle(R_0050_0043__COULD_R_0050_0045__HANDLE)
& has_arg1(R_0050_0043__COULD_R_0050_0045__HANDLE,R_0050_0041__THE_R_0050_0042__HARDWARE)
& has_arg0(R_0050_0043__COULD_R_0050_0045__HANDLE,R_0050_0029__THE_R_0050_0030__CAD_R_0050_0031__PROGRAM)
& r_0050_0029__the_r_0050_0030__CAD_r_0050_0031__program(R_0050_0029__THE_R_0050_0030__CAD_R_0050_0031__PROGRAM)
& has_inv_arg1(R_0050_0029__THE_R_0050_0030__CAD_R_0050_0031__PROGRAM,R_0050_0038__USE) )
& has_arg1(R_0050_0016__THINK,R_0050_0022__BECAUSE)
& r_0050_0022__because(R_0050_0022__BECAUSE)
& has_conj1(R_0050_0022__BECAUSE,R_0050_0024__WERE)
& r_0050_0024__were(R_0050_0024__WERE)
& has_arg0(R_0050_0024__WERE,Z_0050_5008)
& z_0050_5008(Z_0050_5008)
& has_attrib(Z_0050_5008,R_0050_0025__MORE)
& r_0050_0025__more(R_0050_0025__MORE)
& has_r_0050_0026__than(R_0050_0025__MORE,R_0050_0027__512)
& has_conj2(R_0050_0022__BECAUSE,R_0050_0018__BROKE)
& r_0050_0018__broke(R_0050_0018__BROKE)
& has_arg1(R_0050_0018__BROKE,R_0050_0019__THE_R_0050_0020__CAD_R_0050_0021__PROGRAM)
& has_arg0(R_0050_0018__BROKE,R_0050_0017__IT)
& has_arg0(R_0050_0016__THINK,R_0050_0015__I)
& has_r_0050_0010__by__nim(R_0050_0002___APOS_S,R_0050_0013__STANDARDS)
& r_0050_0013__standards(R_0050_0013__STANDARDS)
& has_gen(R_0050_0013__STANDARDS,R_0050_0011__TODAY)
& has_r_0050_0008__on__nim(R_0050_0002___APOS_S,R_0050_0009__THERE)
& has_arg0(R_0050_0002___APOS_S,R_0050_0003__AN_R_0050_0005__LOT)
& r_0050_0003__an_r_0050_0005__lot(R_0050_0003__AN_R_0050_0005__LOT)
& has_r_0050_0006__of(R_0050_0003__AN_R_0050_0005__LOT,R_0050_0007__COMPONENTS)
& has_attrib(R_0050_0003__AN_R_0050_0005__LOT,R_0050_0004__AWFUL) ) ).